The present invention relates to electronic circuits; more particular, to a phase locked loop (PLL) for use in semiconductor devices and integrated circuits.
A PLL is a circuit that generates a periodic output signal having a constant phase and frequency with respect to a periodic input signal. The PLL is widely used in various types of measurements, microprocessors and wireless/wired telecommunication applications. The PLL is included in a circuit such as a phase adjusting circuit, a frequency synthesizer and a clock distribution circuit in a system for outputting signals having a consistent frequency and phase.
FIG. 1 shows a block diagram of a conventional phase-locked loop (PLL). The conventional PLL has a main signal path constituted with a phase-frequency detector 101, a charge pump 102, a loop filter 103 and a voltage-controlled oscillator (VCO) 104 and a feedback signal path constituted with a divider 105. The phase-frequency detector 101 compares a phase of an input reference clock signal 100 having a frequency Fref with a phase of a feedback signal 106 having a frequency Fdiv. Based on a comparison result, the phase-frequency detector 101 generates a comparison signal such as an up signal UP or a down signal DOWN, where the magnitude of the comparison signal indicates a phase difference between the input reference clock signal 100 and feedback signal 106. When the phase of the input reference clock signal 100 leads the phase of the feedback signal 106, the phase-frequency detector 101 generates the signal UP. Otherwise, when the phase of the reference signal 100 lags the phase of feedback signal 106, the phase-frequency detector 101 generates the down signal DOWN. The charge pump 102 generates an amount of positive or negative charge Q based on the comparison signal and supplies the positive or negative charge to the loop filter 103 which operates as an integrator accumulating the amount of charge Q from the charge pump 102. The loop filter 103 generates a loop filtering voltage VLF corresponding to the amount of the charge Q. The loop filtering voltage VLF is supplied to the VCO 104 which generates a periodic VCO output signal 107 whose frequency FVCO is decided by a level of the loop filter voltage VLF, where the VCO output signal 107 is an output signal of the convention PLL.
The VCO output signal 107 is also supplied to the divider 105 for generating the feed back signal 106 by dividing the VCO output signal 107 by an integer N corresponding to an input code CODE. For example, the frequency FVCO of the VCO output signal 105 divided by 2 as a dividing integer is twice as large as the VCO output signal 107 decided by 1. The dividing integer N can be appropriately determined based on the variation of the input code CODE. Then, the VCO output signal 107 having a various frequency can be outputted.
However, characteristics of the conventional PLL can be distorted due to change of the integer N. Especially, the loop filter 103 can be adversely affected due to change of the integer N. In order that the conventional PLL be operated on an adequate frequency margin and locking time, configured values of the loop filter in the conventional PLL should be appropriately adjusted in response to the change of the integer N. That is, capacitances and resistances of elements included in the loop filter 103 must be adjusted.
FIG. 2 shows a loop filter of the conventional PLL in FIG. 1. The loop filter 103 including two capacitors C1 and C2 and a resistor R which operate as a low pass filter. Described above, in response to the change of the dividing integer N of the divider 105, the capacitance of the capacitors C1 and C2 and the resistance of the resistor R must be appropriately adjusted. Accordingly, the operating point of the loop filter 103 can be included.
However, elements, included in the conventional PLL, have fixed values of elements such as the capacitors C1 and C2 and the resistor R. Therefore, although the dividing integer N of the divider 105 is changed, the operating point of the loop filter 103 cannot be adjusted. Finally the conventional PLL can not be operated at optimum operating condition in order to obtain appropriately a frequency margin and a locking time.